This tool automatically generates a template file for a testbench for the simulation of a VHDL entity.
A testbench is a VHDL code that simulates the environment around your DUT (design under test).
The testbench generates stimuli to the inputs of the DUT and allows to check its functionality and outputs within a simulator.
The declarative part of the testbench is quite boring to write, hence the existence of this automatic generator.
The generator is in constant development, but for now it seems to work pretty well for most standard source files,
but it has not yet been extensively tested with a lot of different sources with different writing styles.
Feel free to test it with your files and to report problems to help to improve it.
This is for VHDL only, don't try to paste Verilog code, it will not work ;-)
Simply copy and paste your VHDL code below, then press the Generate button.